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    Technology Jobs for Virtual Machine Monitor (VMM)
  • Engineer 2 Verification (3 - 6 yrs)

    Write verification specifications, verification plans, and documentationDevelop test bench and automate regression plansBe responsible for simulations, verifications, and debugging of logic designs (schematics, RTL)Development of Behavioral models using Verilog and SystemVerilogDevelop Coverage driv...

  • ICT Senior Infrastructure Server Engineer

    Confidential - computerjobs-uk

    We require an ICT Senior Infrastructure Server Engineer for an initial 2 month contract role based on a Client site within the Public Sector in London to start ASAP...Role overview: To support the ICT Infrastructure Manager by undertaking responsibilities associated with the design, development and ...

  • Confidential - naukri

    Hardware Engineers - (Onsite Location- Malaysia): 2-4 years of experience in verification 1) Expertise in System Verilog UVM ( VMM ) 2) Expertise in architecting, design and development of verification environments from scratch 3) Strong Digital design fundamentals 4) Thorough understanding of Proce...

  • Confidential - naukri

    *ASIC Verification and Validation engineer*Hands on knowledge of System Verilog*Hands on working knowledgeof methodologies like VMM, OVM, eRM * Project experience in PCIe, DDR, USB * Strong hands-on experience on SOC projects.

  • Sr. ASIC/ Layout Design Engineer (3 - 8 yrs)

    Confidential - timesjobs

    Work with global Front-End design team and physical design team for large scale ASIC chip physical implementation.Focus on physical design of deep sub-micron GPU chips including block level (full chip) floor planning, timing closure, placeroute, physical verification etc.Responsible for multiple asp...

  • Engineer 2, Verification (3 - 6 yrs)

    Confidential - timesjobs

    Write verification specifications, verification plans, and documentationDevelop test bench and automate regression plansBe responsible for simulations, verifications, and debugging of logic designs (schematics, RTL)Development of Behavioral models using Verilog and SystemVerilogDevelop Coverage driv...

  • Verification Engineer (Sr. / Lead) (4 - 9 yrs)

    Confidential - timesjobs

    He / She will be responsible to execute development and verification activities individually / in team with / without guidance.He/She will be involved in developing Test bench for the Block / Cluster, Test cases, Test plans and Functional and Code coverage closure activities and reviews of documents...

  • Head of Platform Architecture

    Confidential - computerjobs-uk

    Alternative is an AIM listed IT Service provider specialising in the transition to cloud for the UK private and public sector organisations. The role sits at the heart Alternatives go to market strategy leading the technical development of the groups customer facing cloud offering across Private, Hy...

  • System Engineer

    Confidential - Monster_AUS

    System Engineer (Permanent, ACT $100K-$120K + super)We are in search for a System Engineer (mid-level). As part of theMS Solutions team your role will be pivotal in the success of largefederal government infrastructure projects.You will be responsible forsoftware installation, networking, hardware s...

  • Engineer 2, Verification (3 - 6 yrs)

    Confidential - timesjobs

    Minimum of 3 to 6 years of related work experience.Hands on project experience in RTL VerificationStrong knowledge on digital fundamentalsHands on knowledge on Verilog and SystemVerilogHands on knowledge on System Verilog Assertions, Functional Coverage and Scoreboard developmentExperience in C, C++...

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