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    Technology Jobs for Dynamic Random Access Memory (DRAM)
  • SMTS Design Engineer (5 - 10 yrs)

    KEY RESPONSIBILITIESPotential roles of a Microprocessor Performance Engineer include:Benchmark/workload analysis, characterization and optimizationPerformance model development and simulationAPU power and performance tradeoffsMicroarchitecture definition and evaluationJob responsibilities also inclu...

  • SENIOR MEMORY SYSTEM ARCHITECT (5 - 10 yrs)

    RESPONSIBILITIES:- Drive new memory system architectures from DRAM up.- Explore architecture trade-offs in system performance, area, and power consumption.- Develop interconnect (Network-on-chip - NOC) and memory hierarchies for high performance parallel computer architectures (system-on-a-chip SOC)...

  • SR. MEMORY SYSTEM ARCHITECT (5 - 10 yrs)

    - Drive new memory system architectures from DRAM up.- Explore architecture trade-offs in system performance, area, and power consumption.- Develop interconnect (Network-on-chip - NOC) and memory hierarchies for high performance parallel computer architectures (system-on-a-chip SOC).- Add virtualiza...

  • SENIOR ARCHITECT - MEMORY (7 - 12 yrs)

    - Drive new memory system architectures from DRAM up.- Explore architecture trade-offs in system performance, area, and power consumption.- Develop interconnect (Network-on-chip - NOC) and memory hierarchies for high performance parallel computer architectures (system-on-a-chip SOC).- Add virtualiza...

  • SENIOR IP DESIGN ENGINEER (5 - 10 yrs)

    o IP developmento Requirement specification, functional specification, implementation specification creationo Micro-architecture of designo RTL implementation and Linto Synthesis, static timing analysis and power analysisEducation and Experience: Professional Qualificationso BE or ME in Electronics/...

  • Apu Performance Verification Manager (12 - 14 yrs)

    The main roles of this team are to execute architectural definition and trade-off studies, to generate performance projections and to carry out performance verification. The teams key focus is to improve the performance of world-class Accelerated Processing Units (APUs). The APU includes a growing n...

  • IOT Embedded Trainer (2 - 5 yrs)

    Develop/modify/adapt Linux device drivers and board support packages for new processors, memory chips, I/O chipsets, I/O interfaces and boards e.g. x86, ARM, FLASH, DRAM, Ethernet, WiFi, ZigBee, 2G, 3G, CAN, SPI, I2C, I2S,GPIO, USB and PCIe.Develop applications that demonstrate and validate new embe...

  • RTL Design & Verification Engineers (3 - 8 yrs)

    Network packet header parsing, packet classification.WQ manager, QoS support.H/W traffic managerCPU pipeline architecture design, more than 1000 h/w processor. Processorss ISA is Ericssons own design.Memory sub-system, memory controller, DDR3, SRAM, RLDRAM etc, DRAM controllerPCI expressSearch engin...

  • IOT software Trainer (2 - 7 yrs)

    Develop/modify/adapt Linux device drivers and board support packages for new processors, memory chips, I/O chipsets, I/O interfaces and boards e.g. x86, ARM, FLASH, DRAM, Ethernet, WiFi, ZigBee, 2G, 3G, CAN, SPI, I2C, I2S,GPIO, USB and PCIe.Develop applications that demonstrate and validate new embe...

  • SR. Memory System Architect

    RESPONSIBILITIES: - Drive new memory system architectures from DRAM up. - Explore architecture trade-offs in system performance, area, and power consumption. - Develop interconnect (Network-on-chip - NOC) and memory hierarchies for high performance parallel computer architectures (system-on-a-chip S...

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Awards & Accolades for MyTechLogy
Winner of
REDHERRING
Top 100 Asia
Finalist at SiTF Awards 2014 under the category Best Social & Community Product
Finalist at HR Vendor of the Year 2015 Awards under the category Best Learning Management System
Finalist at HR Vendor of the Year 2015 Awards under the category Best Talent Management Software
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