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  • Sigma Allied Services Private Limited - naukri

    Exp: 8 yrs Location : Bangalore - RTL design experience, familiarity with AHB/AXI buses, experience with spyglass(lint), CDC, core and chip integration - Verilog/VHDL RTL/Conformal Verification(LEC) Synthesis (DC) Spyglass (lint, DFT, PM, CLK/RST) - SoC integration flows (integrating multiple IPs a...

  • ASIC Design Engineer (5 - 10 yrs)

    Prolim Solutions India Private Limited - timesjobs

    Around 5+ years of industry experience in ASIC designs and implementation.Hands on experience in VHDL/Verilog coding, Lint tools and Synthesis tools. Should have bus based protocol knowledge, one of PCIe, USB, MIPI or CPUGood communication skill.

  • SENIOR ENGINEER-SOC DESIGN (6 - 8 yrs)

    OPEN-SILICON INC. - timesjobs

    Good in RTL DesignExperience in ARM/AMBA based SoC integrationShould have worked on Verilog/VHDLExperience in Lint, Synthesis, LEC, Constraints generation preferredExposure to DDR/USB/PCIe/SAS/Ethernet/HDMI/MIPI protocols is a plusExposure in doing SOCs

  • RTL DESIGN / INTEGRATION (FOR SINGAPORE) (5 - 10 yrs)

    Tessolve services pvt ltd - timesjobs

    Requirements :Skills Required:SoC Specification to Architecture implementationGood experience in RTL Integration, CDC, Lint, Spyglass, LEC, Synthesis.Experience in one of these is mandatoryResponsibilities :Primary skill - Ethernet, Wi-Fi, Wlan, Memory Controllers, Data Paths, DDR, PCIE.Secondary s...

  • STA/Synthesis (4 - 9 yrs)

    CAMBIO CONSULTING INDIA PVT. LTD. - timesjobs

    Experience in logic/physical Synthesis timing closure at the chip and block level Execute static timing analysis, synthesis, formal verification and power analysis* Analyze results and work with the RTL designers and place / route team to resolve issues* Expertise with STA tools such as Synopsys Pr...

  • Wipro Ltd - naukri

    Key skills required for the job are: ASIC Design (Mandatory) ASIC Synthesis VLSI High Level Description Language - HDLMin 4yrs experience in ASIC design Should have experience on Verilog/VHDL Should have worked on Synthesis, CDC, Lint, TIming analysis Should have good communication skills should ha...

  • RTL Integration (3 - 8 yrs)

    Mirafra Software Technologies Private Limited - timesjobs

    1. Verilog/VHDL RTL/Conformal Verification(LEC) Synthesis (DC) Spyglass (lint, DFT, PM, CLK/RST)2. SoC integration flows (integrating multiple IPs and associated, Understanding of Power Management (voltage domain, power domains, clock domains) OCP and AXI protocols ARM understanding3. Misc.: Debuss...

  • STA Engineers (3 - 8 yrs)

    Cambio Consulting Pvt Ltd - timesjobs

    Experience in logic/physical Synthesis timing closure at the chip and block level Execute static timing analysis, synthesis, formal verification and power analysisAnalyze results and work with the RTL designers and place / route team to resolve issuesExpertise with STA tools such as Synopsys Primet...

  • Software Developer STA/Synthesis (3 - 8 yrs)

    CAMBIO CONSULTING INDIA PVT. LTD. - timesjobs

    Experience in logic/physical Synthesis timing closure at the chip and block level Execute static timing analysis, synthesis, formal verification and power analysis* Analyze results and work with the RTL designers and place / route team to resolve issues* Expertise with STA tools such as Synopsys Pr...

  • STA/Synthesis (3 - 8 yrs)

    CAMBIO CONSULTING PVT. LTD. - timesjobs

    Experience in logic/physical Synthesis timing closure at the chip and block level Execute static timing analysis, synthesis, formal verification and power analysis* Analyze results and work with the RTL designers and place / route team to resolve issues* Expertise with STA tools such as Synopsys Pr...

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