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  • RTL Design

    US Technology International Pvt Ltd - naukri

    Experience range 8-20 Years. Location: Malaysia include block level verification Phy (DSP) and some Mac (control/packet parsing/data path) experience VCS / NCSIM / VERILOG knowledge. Lint / synthesis knowledge Knowledge in NC/VCS simulator tools, spyglass lint checker, Verilog language (NO VHDL) an...

  • Sr. DFT Engineer


    Proven expertise of DFT with multiple tape-outs. Good understanding of synthesis. Strong in DFT verification, UPF experience is a plus. Good understanding of LINT.

  • RTL Engineer

    Pooja Enterprises - naukri

    Digital Design, RTL, micro-architectural background, VHDL/Verilog/SVMIPI, DDR, Ethernet, Networking, Packet processingFEV, Lint, CDC, Timing analysis and bus protocolsSOC level design integration, pin muxing, padring, multi power domain

  • Design Engineer

    Randstad India Limited - naukri

    8+years of exp. in design engineer. Hands on experience in design, synthesis, CDC analysis, Lint flow. Experience in MIPI projects like UFS/UniPro/ CSI/DSI will be added advantage.

  • RTL Integration Specialist

    Incise Infotech - naukri

    - Shoud have at least 2+ years experience in RTL Design and Verification - Should have hands on experience on LINT, CDC, Formality/Conformal - Should be self motivated - Should have good communication skills - Must be a good team player - Should be an early joiner - Salary is not a constraint for d...

  • Sr.rtl Design Engineer


    Developed micro-architecture for a complex block based on top level architecture document. Proficient in RTL implementation using Verilog/VHDL. Proficient in using RTL LINT. Familiarity with RTL synthesis and timing constraint development. Experience in domains like PCIe and DDR3/4 is desirable. Ex...

  • RTL Design Engineer - ASIC

    Premium-Jobs - naukri

    RTL Engineer in -ASIC Flows LINT CDC (Clark Domain Crossing) DRC rule checking Synthesis using RTL compiler - Develop micro-architecture and RTL implementation - Block level/ full chip integration and design. Experience on ASIC - At least 3+ years experience with design, verification and timing too...

  • RTL - Timing (constraints/synthesis/sta)

    Mobiveil Technologies India Private Limited - naukri

    Requirements: Timing (Constraints/Synthesis/STA) TimingASIC Constraint development, Synthesis/ STA. Strong experience in Logic synthesis, STA, Lint and CDC checks, DFT, constraining, physical implementation Hands-on experience in timing analysis Experience in doing SoC level timing analysis Should ...

  • STA / Synthesis Engineers (3 - 8 yrs)

    Cambio consulting india pvt. ltd - timesjobs

    Experience : 3 to 8 Years of Relevant Domain Experience : Experience in logic/physical Synthesis timing closure at the chip and block level Execute static timing analysis, synthesis, formal verification and power analysis Analyze results and work with the RTL designers and place / route team to res...

  • Cypress Semiconductor Technology India Pvt. Ltd - naukri

    Sr Design Engineer who is responsible for the design and development of electronic circuits. Responsibilities include: the design of IP Blocks, circuit and logic simulation, verification, block level and chip level logic integration activities (LINT, Clock Domain Crossing Analysis, UPF, LEC, Synthe...

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