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  • SENIOR ENGINEER-SOC DESIGN (6 - 8 yrs)

    OPEN-SILICON INC. - timesjobs

    Good in RTL DesignExperience in ARM/AMBA based SoC integrationShould have worked on Verilog/VHDLExperience in Lint, Synthesis, LEC, Constraints generation preferredExposure to DDR/USB/PCIe/SAS/Ethernet/HDMI/MIPI protocols is a plusExposure in doing SOCs

  • ASIC Design Engineer (5 - 10 yrs)

    Prolim Solutions India Private Limited - timesjobs

    Around 5+ years of industry experience in ASIC designs and implementation.Hands on experience in VHDL/Verilog coding, Lint tools and Synthesis tools. Should have bus based protocol knowledge, one of PCIe, USB, MIPI or CPUGood communication skill.

  • STA/Synthesis (4 - 9 yrs)

    CAMBIO CONSULTING INDIA PVT. LTD. - timesjobs

    Experience in logic/physical Synthesis timing closure at the chip and block level Execute static timing analysis, synthesis, formal verification and power analysis* Analyze results and work with the RTL designers and place / route team to resolve issues* Expertise with STA tools such as Synopsys Pr...

  • STA/Synthesis (3 - 8 yrs)

    CAMBIO CONSULTING PVT. LTD. - timesjobs

    Experience in logic/physical Synthesis timing closure at the chip and block level Execute static timing analysis, synthesis, formal verification and power analysis* Analyze results and work with the RTL designers and place / route team to resolve issues* Expertise with STA tools such as Synopsys Pr...

  • STA Engineers (3 - 8 yrs)

    Cambio Consulting Pvt Ltd - timesjobs

    Experience in logic/physical Synthesis timing closure at the chip and block level Execute static timing analysis, synthesis, formal verification and power analysisAnalyze results and work with the RTL designers and place / route team to resolve issuesExpertise with STA tools such as Synopsys Primet...

  • Android App / Software Developer (5 - 8 yrs)

    Endeavor IT Solution - timesjobs

    Essential Skills:--Strong fundamentals in Core Java, OOPS and various Android Components and APIs.-Must have good problem solving, debugging and optimization skills.-Good understanding of DBMS, SQL, data structures, algorithms complexity.Add On Experience and Skills:--Work with IntentServices, Loca...

  • PE,Logic Design Engineering (10 - 15 yrs)

    Rambus.com - timesjobs

    Develop micro-architecture and RTL design for digital components for SERDES IPs such as PCSGenerating soft-macros (RTL) to be used in test-chip/product designsSetup and analysis of lint, synthesis, timing and DFT reportsSupport Protocol validation activitiesQualifications:Skills/Qualifications:Elec...

  • STA Engineers (3 - 8 yrs)

    Cambio Consulting Pvt Ltd - timesjobs

    Experience in logic/physical Synthesis timing closure at the chip and block level Execute static timing analysis, synthesis, formal verification and power analysisAnalyze results and work with the RTL designers and place / route team to resolve issuesExpertise with STA tools such as Synopsys Primet...

  • Pr/staff SOC Design - Synthesis (8 - 13 yrs)

    Classic Search Pvt Ltd - timesjobs

    Expertise in Synthesis, Formal Verification, and Static Timing Analysis, preferably with Synopsys tools.Expertise in RTL coding and simulation using Verilog/SystemVerilogKnowledgeable in Chip level Design and Integration activitiesProficiency in common UNIX scripting languages (Perl, Python, Tcl, c...

  • Android App / Software Developer (5 - 8 yrs)

    Endeavor IT Solution - timesjobs

    Essential Skills:--Strong fundamentals in Core Java, OOPS and various Android Components and APIs.-Must have good problem solving, debugging and optimization skills.-Good understanding of DBMS, SQL, data structures, algorithms complexity.Add On Experience and Skills:--Work with IntentServices, Loca...

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