MyPage is a personalized page based on your interests.The page is customized to help you to find content that matters you the most.


I'm not curious
Largest dedicated platform of global Information Technology (IT) job search and career opportunities for IT professionals.If you are hiring IT professionals, post IT & Technology Job Descriptions for free. IT jobs can be viewed anytime from anywhere using mobile devices.

    Filter Results:
  • VERIFICATION ENGINEER (6 - 9 yrs)

    MEC Concepts India Private Limited - timesjobs

    1) Hands on System Verilog and UVM/OVM .2) Have worked at least on one complex project like USB,PCIe, SATA, MIPI,DDR etc. ( not just AHB, APB, I2C,SPI, UART etc.).3) Have done at least one project starting from test planning to writing test environment.To be responsible for managing technology in p...

  • Staff Verification Engineer (Architecture Verification) (8 - 13 yrs)

    ARM Embedded Technologies Private Ltd - timesjobs

    Able to provide technical leadership, with an ability to drive forward innovation in technical areas.Ability to lead and motivate highly skilled engineers.Ability to workwell as part of a team both locally, and also with remote or multi-site teamsProfessional and enthusiastic approach to workJob Re...

  • Senior Verification Engineer (Architecture Verification) (4 - 9 yrs)

    ARM Embedded Technologies Private Ltd - timesjobs

    Able to work alone as well as contributing toa project team.Demonstrate ownership for the assigned part of the project work, investigations and feasibility studies.Understands the process of product development.Job RequirementsCharacteristics RequirementsUnderstand architecture specifications, veri...

  • Senior Verification Engineer System Verilog (3 - 8 yrs)

    Qusol Consultancy Private Limited - timesjobs

    Senior Verification EngineerSystem Verilog, OVM / UVM Skillset Must Have Block and Top level verification know-how Verification Plan Development System Verilog/OVM or UVM Testbench Development VHDL/Verilog simulation and debug Scripting Nice to have HVL: Specman is a plus End to End RTL Functional ...

  • Senior Verification Engineer System Verilog (3 - 8 yrs)

    Qusol Consultancy Private Limited - timesjobs

    Senior Verification EngineerSystem Verilog, OVM / UVM Skillset Must Have Block and Top level verification know-how Verification Plan Development System Verilog/OVM or UVM Testbench Development VHDL/Verilog simulation and debug Scripting Nice to have HVL: Specman is a plus End to End RTL Functional ...

  • AMS Verification Engineer

    Sankalp Semiconductor Pvt. ltd - naukri

    Desired Profile Specs : AMS Verification engineers with 5+ of relevant work experience. Should have worked using Verilog A and System Verilog. Should be able to model, run formal verification from Specs. Digital Skills: Good understanding on Verilog, System Verilog with UVM Setting up / running / d...

  • Verification Engineer (5 - 8 yrs)

    ASSURE CONSULTING SERVICES PRIVATE LIMITED - timesjobs

    The person should be an Electrical, Electronics or Computer Science Engineer with very good understanding of HDLs (Verilog and/ or VHDL) and Low Power. He/ she should have prior experience in simulation using these languages. He/ she should have a good working knowledge of EDA tools (Cadence/ Other...

  • Sr. Verification Engineer

    LOGICBULLS CONSULTING PRIVATE LIMITED - naukri

    Participated in atleast 3 tapeouts using UVM/OVM Methodology. Must have experience developing test plan, test benches and writing test cases. Must have ability to debug and root cause failures. Familiarity with UPF or CPF lower power flow would be a big plus. Experience verifying PCIe and DDR3/4 is...

  • Senior/lead/ Verification Engineer

    Sivaltech Pvt. Ltd. - naukri

    Minimum 3 years of experience in IP or SOCs Verification Experienced with development of UVM, OVM, VMM and/or System Verilog, Verilog test benches and usage of simulation tools/debug environments. Strong understanding of state of the art of verification techniques, including assertion and metric-dr...

  • Design Verification Engineer (3 - 8 yrs)

    Agnisys Technology Pvt. Ltd. - timesjobs

    System Verilog, Verilog, UVM/VMMExperience inat system level and block level verification.Expert in System Verilog and OVM/UVM based verification.Strong experience in ASIC design/validation experience in front end processes including RTL development, functional and performance verification.Expert i...

Awards & Accolades for MyTechLogy
Winner of
REDHERRING
Top 100 Asia
Finalist at SiTF Awards 2014 under the category Best Social & Community Product
Finalist at HR Vendor of the Year 2015 Awards under the category Best Learning Management System
Finalist at HR Vendor of the Year 2015 Awards under the category Best Talent Management Software
Hidden Image Url

Back to Top