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  • Design and Verification engineer (5-10 yrs)

    Ashtopus Consulting - Kuala Lumpur - HeadHonchos

    RTL Design: Candidates with a degree in Electrical Engineering with 5+ years of experience in Micro Architecture, RTL Development and debugging. Ideal candidate will have the skills in PCIe Link layer development and good understanding of the PCIe protocol. Minimum skills expected: Verilog , System...

  • Analog Mixed Signal Verification Engineer (5-11 yrs)

    Kaizen SRA Technologies - Malaysia-Other - HeadHonchos

    : Validation of mixed signal features in the IO example DDRIO, OPIO, eOPIO, Phy IO Validation of functional interactions between analog and digital components Experience digital validation and analog validation, as senior as you can. Know to debug/triage logic design issue or analog design issue Fo...

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