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  • Expert System Verilog Professionals (10 - 15 yrs)

    Client Of Roljobs Technology Services Pvt Ltd - timesjobs

    Wed love to hear from you if:You have total working experience of 10-15 Years.You have experience in SOC verification with exposure to all stages of the verification flow.You have hands on working experience in System Verilog.You have experience with one or more methodologies like UVM/ OVM/ VMM.Sho...

  • Senior Verification Engineer - System Verilog (5 - 10 yrs)

    WhizChip Design Technologies Pvt. Ltd - timesjobs

    Description Experience in System Verilog.Exposure / experience in verification methodologies like OVM/UVMExpertise in sub-system/SOC verificationsBuilding verification environments using high level languages like System Verilog, OVM/UVM methodologies.Must be good in writing tests, automating regres...

  • Expert System Verilog Professionals (10 - 15 yrs)

    CLIENT OF ROLAND & ASSOCIATES - timesjobs

    You have total working experience of 10-15 Years.You have experience in SOC verification with exposure to all stages of the verification flow.You have hands on working experience in System Verilog.You have experience with one or more methodologies like UVM/ OVM/ VMM.Should be exceptional interperso...

  • Senior Verification Engineer System Verilog (3 - 8 yrs)

    Qusol Consultancy Private Limited - timesjobs

    Senior Verification EngineerSystem Verilog, OVM / UVM Skillset Must Have Block and Top level verification know-how Verification Plan Development System Verilog/OVM or UVM Testbench Development VHDL/Verilog simulation and debug Scripting Nice to have HVL: Specman is a plus End to End RTL Functional ...

  • Expert System Verilog Professionals (10 - 15 yrs)

    CLIENT OF ROLAND & ASSOCIATES - timesjobs

    You have total working experience of 10-15 Years.You have experience in SOC verification with exposure to all stages of the verification flow.You have hands on working experience in System Verilog.You have experience with one or more methodologies like UVM/ OVM/ VMM.Should be exceptional interperso...

  • Design Verification System Verilog (6 - 10 yrs)

    KBS consultants - timesjobs

    Should have worked on SOC level verification on at least one project with constrained random methodology (eRM / VMM / OVM).Proficiency in one or more HVLs System Verilog, C++, Vera, e, System C, Test Builder is a must.Strong domain knowledge on one or more of PCIe, USB, Ethernet, ARM, AHB / AXI, AM...

  • Design Verification System Verilog (6 - 10 yrs)

    KBS consultants - timesjobs

    Should have worked on SOC level verification on at least one project with constrained random methodology (eRM / VMM / OVM).Proficiency in one or more HVLs System Verilog, C++, Vera, e, System C, Test Builder is a must.Strong domain knowledge on one or more of PCIe, USB, Ethernet, ARM, AHB / AXI, AM...

  • Senior Verification Engineer System Verilog (3 - 8 yrs)

    Qusol Consultancy Private Limited - timesjobs

    Senior Verification EngineerSystem Verilog, OVM / UVM Skillset Must Have Block and Top level verification know-how Verification Plan Development System Verilog/OVM or UVM Testbench Development VHDL/Verilog simulation and debug Scripting Nice to have HVL: Specman is a plus End to End RTL Functional ...

  • Expert System Verilog Professionals (10 - 15 yrs)

    Roljobs Technology Services Pvt Ltd - timesjobs

    You have total working experience of 10-15 Years.You have experience in SOC verification with exposure to all stages of the verification flow.You have hands on working experience in System Verilog.You have experience with one or more methodologies like UVM/ OVM/ VMM.Should be exceptional interperso...

  • Verification Engineers System Verilog,UVM (4 - 9 yrs)

    Test and Verification Solutions Limited - timesjobs

    EducationB.E in Computer or Electronics EngineeringM.Tech or PhD an advantageSkillsetMust HaveBlock and Top level verification know-howVerification Plan DevelopmentSystem Verilog/OVM or UVMTestbench DevelopmentVHDL/Verilog simulation and debugScriptingNice to haveHVL: Specman is a plusEnd to End RT...

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