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  • Expert System Verilog Professionals (10 - 15 yrs)

    CLIENT OF ROLAND & ASSOCIATES - timesjobs

    Our client is looking for a Verification Specialist to join their exclusive team in Bangalore. They are looking for experts who are dynamic, self motivated and out-of-the-box thinkers, to join their team.Wed love to hear from you if:You have total working experience of 10-15 Years.You have experien...

  • Senior Verification Engineer System Verilog (3 - 8 yrs)

    Qusol Consultancy Private Limited - timesjobs

    Senior Verification EngineerSystem Verilog, OVM / UVM Skillset Must Have Block and Top level verification know-how Verification Plan Development System Verilog/OVM or UVM Testbench Development VHDL/Verilog simulation and debug Scripting Nice to have HVL: Specman is a plus End to End RTL Functional ...

  • Design Verification System Verilog (6 - 10 yrs)

    KBS consultants - timesjobs

    Should have worked on SOC level verification on at least one project with constrained random methodology (eRM / VMM / OVM).Proficiency in one or more HVLs System Verilog, C++, Vera, e, System C, Test Builder is a must.Strong domain knowledge on one or more of PCIe, USB, Ethernet, ARM, AHB / AXI, AM...

  • Design Verification System Verilog (6 - 10 yrs)

    KBS consultants - timesjobs

    Should have worked on SOC level verification on at least one project with constrained random methodology (eRM / VMM / OVM).Proficiency in one or more HVLs System Verilog, C++, Vera, e, System C, Test Builder is a must.Strong domain knowledge on one or more of PCIe, USB, Ethernet, ARM, AHB / AXI, AM...

  • Senior Verification Engineer System Verilog (3 - 8 yrs)

    Qusol Consultancy Private Limited - timesjobs

    Senior Verification EngineerSystem Verilog, OVM / UVM Skillset Must Have Block and Top level verification know-how Verification Plan Development System Verilog/OVM or UVM Testbench Development VHDL/Verilog simulation and debug Scripting Nice to have HVL: Specman is a plus End to End RTL Functional ...

  • Design Verification Engineer - IP/ Soc/ Verilog

    Tech Vulcan - naukri

    Please find the below mentioned job description : - Hands on experience on IP/ SoC verification flow - Hands on experience on System Verilog/ UVM/OVM - Good Knowledge on AMBA/PCIE /ETHERNET/ ARMCORTEX/MIPI/ SATA/USB - Knowledge of scripting language like Perl, Shell, TCL or Python. Experience : 4+Y...

  • Senior Verification Engineer System Verilog (3 - 8 yrs)

    Qusol Consultancy Private Limited - timesjobs

    Senior Verification EngineerSystem Verilog, OVM / UVM Skillset Must Have Block and Top level verification know-how Verification Plan Development System Verilog/OVM or UVM Testbench Development VHDL/Verilog simulation and debug Scripting Nice to have HVL: Specman is a plus End to End RTL Functional ...

  • Expert System Verilog Professionals (10 - 15 yrs)

    CLIENT OF ROLAND & ASSOCIATES - timesjobs

    You have total working experience of 10-15 Years.You have experience in SOC verification with exposure to all stages of the verification flow.You have hands on working experience in System Verilog.You have experience with one or more methodologies like UVM/ OVM/ VMM.Should be exceptional interperso...

  • Senior Verification Engineer / Project Lead System Verilog (3 - 8 yrs)

    Test and Verification Solutions Limited - timesjobs

    EducationB.E in Computer or Electronics EngineeringM.Tech or PhD an advantageSkillsetMust HaveBlock and Top level verification know-howVerification Plan DevelopmentSystem Verilog/OVM or UVMTestbench DevelopmentVHDL/Verilog simulation and debugScriptingNice to haveHVL: Specman is a plusEnd to End RT...

  • Verification with USB and System Verilog (4 - 7 yrs)

    Qusol Consultancy Private Limited - timesjobs

    This requirement is for our fast-growing Technology client that specializes in creation of Intellectual Properties, Frameworks and Solutions for the Networking, Enterprise and Device Mobility markets. Verification Engineers (Openings - 2) 4 to 7 years experience, Location - Chennai Strong UVM, Syst...

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