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  • RTL Design Engineer - Verilog

    Connectpro Mgmt Pvt Ltd - naukri

    Job Description: - You will be responsible for IP / sub-system level micro-architecture development and RTL coding. - Prepare block/sub-system level timing constraints. - Integrate IP/sub-system. - Perform basic verification either in IP Verification environment or FPGA. Desired Skills and Experien...

  • ASIC Verification Engineer - System Verilog HVL

    Premium-Jobs - naukri

    - Total 3- 8 years of experience required in ASIC Verification. - Candidate will be involved in developing Test bench for the Block / Cluster, Test cases, Test plans and Functional and Code coverage closure activities and reviews of documents and code. - Candidate will be individually responsible f...

  • Expert System Verilog Professionals (10 - 15 yrs)

    CLIENT OF ROLAND & ASSOCIATES - timesjobs

    Our client is looking for a Verification Specialist to join their exclusive team in Bangalore. They are looking for experts who are dynamic, self motivated and out-of-the-box thinkers, to join their team.Wed love to hear from you if:You have total working experience of 10-15 Years.You have experien...

  • ASIC Verification Engineer - System Verilog HVL

    Premium-Jobs - naukri

    - Total 3- 8 years of experience required in ASIC Verification. - Candidate will be involved in developing Test bench for the Block / Cluster, Test cases, Test plans and Functional and Code coverage closure activities and reviews of documents and code. - Candidate will be individually responsible f...

  • Asic/fpga Verification Engineer - System Verilog

    Innovision Inc - naukri

    Experience: 04-11 Years Job Location:Bangalore Job Description :- - Verification of high speed ASIC/FPGA designs - Block/subsystem/chip level functional verification - Implement verification environment independently using high level verification - languages like System Verilog - Communicate and co...

  • Senior Verification Engineer System Verilog (3 - 8 yrs)

    Qusol Consultancy Private Limited - timesjobs

    Senior Verification EngineerSystem Verilog, OVM / UVM Skillset Must Have Block and Top level verification know-how Verification Plan Development System Verilog/OVM or UVM Testbench Development VHDL/Verilog simulation and debug Scripting Nice to have HVL: Specman is a plus End to End RTL Functional ...

  • Design Verification System Verilog (6 - 10 yrs)

    KBS consultants - timesjobs

    Should have worked on SOC level verification on at least one project with constrained random methodology (eRM / VMM / OVM).Proficiency in one or more HVLs System Verilog, C++, Vera, e, System C, Test Builder is a must.Strong domain knowledge on one or more of PCIe, USB, Ethernet, ARM, AHB / AXI, AM...

  • Design Verification Engineer - IP/ Soc/ Verilog

    Tech Vulcan - naukri

    Please find the below mentioned job description : - Hands on experience on IP/ SoC verification flow - Hands on experience on System Verilog/ UVM/OVM - Good Knowledge on AMBA/PCIE /ETHERNET/ ARMCORTEX/MIPI/ SATA/USB - Knowledge of scripting language like Perl, Shell, TCL or Python. Experience : 4+Y...

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