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VLSI CAD Logic to Layout

Course Summary

A modern VLSI chip has a zillion parts -- logic, control, memory, interconnect, etc.  How do we design these complex chips?  Answer: CAD software tools.  Learn how to build these tools in this class.


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    Course Syllabus

    Topics covered will include: Computational boolean algebra; logic verification; logic synthesis (2-level and multi-level); technology mapping; timing analysis; ASIC placement and routing.

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    Recommended Background

    Programming experience (C++, Java) and basic knowledge of data structures and algorithms.  An understanding of basic digital design:  Boolean algebra, Kmaps, gates and flip flops, finite state machine design.  Linear algebra and calculus at the level of a junior or senior in engineering.  Exposure to basic VLSI at an undergraduate level is nice -- but it’s not necessary.  We will keep the course self-contained, but students with some VLSI will be able to skip some background material.

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    Course Format

    The class will consist of lecture videos, which are between 15 and 20 minutes in length.  There will also be standalone problem sets (homeworks) that are not part of video lectures, a few programming assignments, and a (not optional) final exam.

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    Suggested Reading

    The course is designed to be self-contained.  However, we will offer pointers to original source material, i.e., papers in conferences and journals.  This area lacks a single, established “front-to-back” text, that covers logic and layout, as well as representation, optimization, synthesis and verification.  So, we will work to be as complete as possible in the lectures.


Course Fee:
Free

Course Type:

Self-Study

Course Status:

Active

Workload:

1 - 4 hours / week

This course is listed under Development & Implementations Community

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