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Course Summary

BUILDING A CHIP IS LIKE BUILDING A CITY !


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    Course Syllabus

    • GENERATED CLOCKS DEFINITION AND CREATION
      • DEFINE GENERATED CLOCK FOR DIVIDE-BY-2 CIRCUIT
      • GENERATED CLOCKS USING MASTER CLOCK EDGES
      • GENERATED CLOCK WAVEFORM DERIVATION
      • GENERATED CLOCK WITH SHIFTED EDGE
    • BASICS OF MOS TRANSISTOR
      • INTRODUCTION TO VLSI ACADEMY
      • GATE VOLTAGE AND ACCUMULATION OF NEGATIVE CHARGE
      • N-CHANNEL FORMATION BETWEEN SOURCE AND DRAIN
      • IMPACT OF SUBSTRATE POTENTIAL ON THRESHOLD VOLTAGE (VT)
    • NOISE MARGIN
      • INTRODUCTION TO NOISE MARGIN
      • NOISE MARGIN VOLTAGE PARAMETERS
      • NOISE MARGIN EQUATIONS AND SUMMARY
    • ON-CHIP VARIATION (OCV)
      • SOURCES OF VARIATION - ETCHING PROCESS
      • SOURCES OF VARIATION - OXIDATION AND DELAY-RESISTANCE RELATIONSHIP
      • DELAY, RESISTANCE AND DRAIN CURRENT RELATIONSHIP
    • SETUP & HOLD TIMING ANALYSIS
      • INITIAL TIMING ANALYSIS AND INTRODUCTION TO FLOP SETUP TIME
      • SETUP TIMING ANALYSIS WITH JITTER AND REAL CLOCKS
      • INTRODUCTION TO SLACK AND HOLD TIMING ANALYSIS
      • HOLD TIMING ANALYSIS CONCLUDED
    • OCV TIMING AND PESSIMISM REMOVAL
      • SETUP TIME TEXTUAL REPRESENTATION WITH EXAMPLE
      • OCV BASED SETUP TIMING ANALYSIS
      • SETUP TIMING ANALYSIS AFTER PESSIMISM REMOVAL
      • HOLD TIME TEXTUAL REPRESENTATION WITH EXAMPLE
      • HOLD TIMING ANALYSIS AFTER PESSIMISM REMOVAL


Course Fee:
Free

Course Type:

Self-Study

Course Status:

Active

Workload:

1 - 4 hours / week

This course is listed under Development & Implementations and Operating Systems Community

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