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VLSI Academy - Clock Tree Synthesis

Course Summary


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    Course Syllabus

      • Introduction to Clock Tree Synthesis
    • Clock Tree Quality Check Parameters
      • Skew and Pulse Width Check
      • Duty Cycle and Latency Check
      • Latency and Power Check
      • Power Check Continued
      • Power and Crosstalk Quality Check
      • Delta Delay Quality Check
      • Glitch Quality Check
    • H - Tree
      • H-Tree Algorithm and Skew Check
      • H-Tree Pulse Width and Duty Cycle Check
      • H-Tree Latency and Power Check
    • Clock Tree Modelling and Observations
      • Clock Tree Modelling
      • Clock Tree Building
      • Clock Tree Buffering
      • Clock Tree Observations
    • Buffered H - Tree
      • H-Tree Buffering Observations
      • H-Tree Skew Check
      • H-Tree Pulse Width Check and Issues with Regular Buffers
      • CMOS Inverter PMOS/NMOS Switching Resistance Difference
      • CMOS Inverter PMOS/NMOS Matching Switching Resistance Solution
      • H-Tree with Clock Buffers and Pulse Width Check
      • H-Tree Duty Cycle, Latency and Power Checks
      • Dynamic Power and Short Circuit Power
      • Leakage Power
    • Clock Tree Optimization Checklist
      • Optimization Checklist
      • Short Circuit Current Reduction Technique
      • Leakage Current Reduction Technique
      • Clock Tree Optimized
      • Optimized Clock Tree Power And Latency Check
    • Uneven Spread of Clock Endpoints
      • Clock Tree for Uneven Spread of Clock End Points
      • Logical to Physical Connections
      • Checklist
      • Advanced H-Tree for Million Flop clock endpoints with uneven spread
    • Power Aware Clock Tree Synthesis
      • Introduction to clock gating cells
      • Introduction to Delay Tables
      • Delay Table Usage - I
      • Delay Table Usage - II
      • Clock Gating Technique using AND Gate and Skew Issue
      • Solution to Skew Issue
      • Clock Gating technique using both AND and OR gate
      • Clock Gating Technique using universal NAND gate
      • Clock Gating Technique on real Chip and its impact on Power
    • Static Timing Analysis
      • Setup Timing Analysis with Real Clocks
      • Introduction to Data Arrival Time, Data Required Time and Slack
      • Impact of unbalanced Skew on Setup Time
      • Hold Timing Analysis with Real Clocks
      • Impact of unbalanced Skew on Hold Time
    • Summary
      • Topics Learned and More to come !!
    • Interview Questions
      • Skew
      • Buffer Levels
      • Latency
      • Clock Gating
      • Setup Slack
      • Setup Slack - I
      • Short Circuit Power
      • Delay Table
      • Leakage Current
      • Total Chip Power

Course Fee:
USD 49

Course Type:


Course Status:



1 - 4 hours / week

This course is listed under Open Source , Development & Implementations and Operating Systems Community

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