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SOC Verification using SystemVerilog

Course Summary

A comprehensive course that teaches System on Chip design verification concepts and coding in SystemVerilog Language

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    Course Syllabus

    • Welcome to Course - Introduction
      • Introduction and Overview
      • Introduction to SOC and VLSI design flows
      • Course Resources
      • Testing Awareness before we start
    • Verification Concepts Explained
      • Verification - What, Why and How ?
      • Verification - Planning, Approaches, Metrics
      • Verification Methodologies - Simulation, Formal, Assertions
      • Directed vs Constrained Random Verification - Coverage
      • Other Trends - HW+SW Verification, Emulation
      • Test your Verification Concepts now
    • Introduction to System Verilog Language
      • History and Language usage overview
      • Language Constructs - Data types and Operators
      • Language Constructs - Loops and Control Flows
      • Tasks and Functions
      • Arrays and Queues
      • Test Your System Verilog Language Basics now
    • Basic SV TB - Connecting to your design
      • Interfaces
      • Clocking Blocks
      • Program Blocks
      • Direct Programming Interface (DPI)
      • Test - How much more you know now !
    • SV - OOP concepts and Randomization
      • Basic OOP Concepts
      • System Verilog Classes Explained
      • Virtual Interfaces
      • Random Constraints and usages - Part 1
      • Random Constraints - Part 2
      • Test - What have you learned more now ?
    • Threads and Inter Process Communication
      • Processes and Threads in System Verilog
      • System Verilog Mailboxes
      • Synchronization - Events and Semaphores
      • Test your knowledge now on Advanced System Verilog
    • Project Assignment - Building a Testbench for Ethernet Switch
      • Exercise 1: Case Study on a Design to be verified
      • Exercise 2: Coding exercise to build a Design to be Verified OR Review example
      • Exercise 3: Coding Interfaces and Clocking Blocks to connect
      • Exercise 4: Building Class based Testbench components
      • Exercise 5: Connecting all TB components using mailboxes
      • Exercise 6: Build the top TB with DUT, compile and simulate
    • Introduction to Verification Methodologies
      • Standard Verification Methodologies - Need and evolution
      • Introduction to concept of OVM and UVM
    • Course Wrapup and Summary
      • Summary and learnings and future topics
      • Final Test - Are you ready for a Verification Job now?

Course Fee:

Course Type:


Course Status:



1 - 4 hours / week

This course is listed under Development & Implementations and Networks & IT Infrastructure Community

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