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Location Milpitas, United States
Posted 08-January-2019
The position is responsible for completing whole ASIC design cycle. Candidate should have experience in the following: RTL coding; RTL simulation; Test bench set up; Logic synthesis using Synopsys DC compiler; static logic timing analysis using Synopsys/Primetime; Post layout timing simulation with sdf file back annotation; ATPG and Scan insertion for production testing; and knowledge in FPGA generation and testing. Logic design experience in the following field is preferred: 2D or 3D graphics, video display controller, DRAM/cache controller, MPEG or JPEG video controller and high speed interface (PCI Express, USB 3.0/2.0, USB Host, Ethernet). Familiar with Microprocessors (ARM, 8051, ARC) and associated bus interfaces (APB, AHB, AXI, BVCI).

* Experience with 3rd party IP integration and testbench generation.
* Experience in programming/scripting languages like Perl, TCL, and UNIX shell.
* Experience with CDC and linting.
* Hand-on experience in logic synthesis, P&R, timing closure, and DFT insertion is a plus.
* Good knowledge of FPGA tool flow (Xilinx or Altera) and prototype validation/bring-up is a plus.
* Knowledge of C/C++ programming, Computer architecture and SoC Chip design flow.


* BSCS, BSCE, BSEE or equivalent, MSEE preferred.
* 5+ years of experience.
* Ability to communicate and work well in a team environment.
* Ability to work with minimal supervision.

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