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AmiSign Technologies - Senior Design Verification Engineer - Python/Verilog (5-10 yrs)

Location Bangalore, India
Posted 18-June-2019

Job Responsibilities :

-Evaluate, utilize existing and develop new verification infrastructure frameworks, tools, and methodologies to enhance the verification process for efficiency and quality

-Consulting design teams on verification best practices and approaches and providing the right solutions

-Training, deployment and support of verification methodologies within organization

-Engaging with EDA vendors to influence their development roadmaps to meet organizations requirements into the future

Minimum Qualifications :

-BTech/MTech degree in Electrical/Electronics/VLSI with 5-10 years of experience from reputed institutes

-Expert in automation and scripting languages like Perl, Python and shell scripting

-Strong hands on experience in Cadence tools like Incisive, Xcelium, IMC,Vmanager and Jasper(good to have)

-Proficient in Version control systems: Perforce, SVN, SOS

-Proficient in Verilog, System Verilog and UVM

-Proficient in GLS, Coverage methodology and mixed signal simulations is an added advantage

-Ability to manage multiple tasks and work effectively in a fast-paced environment

-Able to communicate effectively both written and verbal

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