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Mirafra Technologies - DFT Engineer - MBIST/ATPG (3-10 yrs)

Location Bangalore, India
Posted 18-June-2019
Description

JD :


- Scan insertion, MBIST, Boundary scan, JPAG,EDT insertion.

- Block level Test pattern Generation (ATPG) and simulation

- Ppst Silicon debug support experience

- Tools experience: VCS/NCSim/Modelsim

- Compliers: Fastscan/ Testkompress /DFTAdvisor/Spyglass

- Scripting Skills:Perl/TCL

- DFT architecture definition w.r.t. test time/cost, coverage, test power.

- Good experience/concept on all aspect of DFT i.e. SCAN/ATPG, MBIST, Boundary Scan.

- DFT logic integration and verification.

- Experience on debugging low coverage.

- Gate Level DFT verification with and without timing.

- Experience of leading small DFT team is plus.

- Good experience on EDA tools of reputed vendor like Mentor, Synopsis.

- LBIST experience is plus.

- DFT mode STA and timing closer support.

- Familiar to Verilog and RTL simulation.

- Strong knowledge and experience in Scan Insertion, TestKompression, ATPG, Memory BIST and JTAG at IC

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