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CPU Verification Engineer - System Verilog

Location Bangalore, India
Posted 04-December-2019

Must have :

- Experience in verification in the areas of deep pipeline CPU verification.

- Experience in Out of Order Pipeline/ Memory Management/Coherency Protocol/Instruction/Data Cache/ Level 2 Cache/Virtualization/Hypervisor mode/Floating point verification.

- Strong SV fundamentals :

a) Assertions driven verification

b) Coverage driven verification

- Assembly programming at least with one ISA (x86, ARC, ARC, etc)

- Computer Architecture

- AXI/AHB protocols

- Familiar with UVM

Good to have :

- Knowledge on RISCV-ISA & RISCV-Privileged Specifications

- Strong Knowledge in UVM

- PERL Scripting

Expected Roles :

- Need to Develop the Test plans for a given feature by understanding specifications/interacting with RTL designers.

- Need to develop both ASM and SV tests as required as per Testplan.

- Need to develop the assertions/checker as required.

- Need to develop the complete coverage for a given feature and should be able to close it with sign-off metrics.

- Should be able to develop the entire unit level testbench in SV using UVM from scratch.

Awards & Accolades for MyTechLogy
Winner of
Top 100 Asia
Finalist at SiTF Awards 2014 under the category Best Social & Community Product
Finalist at HR Vendor of the Year 2015 Awards under the category Best Learning Management System
Finalist at HR Vendor of the Year 2015 Awards under the category Best Talent Management Software
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