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System Validation Engineer

Location Menlo Park, United States
Posted 14-August-2020

System Validation Menlo Park CA
USC/GC/H4EAD on w2
Writing C++ System Level tests targeting the CPU/DSP/CNN cores in C++
7+ years of industrial experience.
Writing CPP Performance and Power system-level use-cases
Work on FPGA and Emulation scripts and flows for system validation, to increase
productivity across the team Work on post-silicon bringup and flows Work
closely with Algorithm engineers, DV engineers, Architects and Designers to
come up with system level use-case scenarios Work closely with Design
Verification to enhance and augment verification for IPs on FPGA and/or
Emulation platforms
Work closely with Firmware, Reference Modeling, and Software engineers to
assist software development and debug
What are the must have non-negotiable requirements for this role?
Experience in CPP for writing system level test-cases for SoC like IP
Experience in scripting languages such as Python, TCL etc Experience running
tests on FPGA and/or Emulation platforms for SoC like IP Experience in post-
silicon bringup and flows for SoC like IP Experience with lab system debug with
logic analyzers, scopes, meters, etc Experience in performance evaluation and
modeling for SoC like IP Experience in power tests and evaluation on
prototyping platforms Familiarity with AMBA protocol, OCP protocol Familiarity
in System Verilog for design and verification - for debugging
SOC ASIC target, but we are using a FPGA and Emulator, for silicon
Verification - writing system-level tests running on the CPU and/or DSP which
run on FPGA/Emulator.
Is a hardware (either RTL or Verification) or a firmware / software (system
software/firmware, drivers) background a closer fit to the projects needs?A
mix - since its pre-silicon verification, writing FW like tests, for system
level validation.
Skills: What are the nice to have details for this role?
Performance modeling and evaluation
Knowledge of OS kernel and experience in driver development Familiarity with
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