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Senior Analog Design Engineer

Location Penang , , Malaysia
Posted 19-March-2021

Job Description :
Job Description
Design and development of mixedsignal circuits such as High Speed TX and RXVarious type of compensation circuitry equalizers DLL clocking circuitry such as duty cycle detection correction on die voltage regulators DAC ADC Voltage references power gates powergood high speed level shifter ESD Clamps and View observation circuitryOwn design verification plans covering functional performance and reliability meeting high volume manufacturing requirementParticipate in circuit design review preparing circuit constraint through CCM as guideline for Mask Designers on layout implementation and floorplan review reliability results review and audit with QREResponsible on collateral generation such as Integration Guide Timing model Noise model RTLBMOD model Power data IBIS model ICCT profile RV report on circuits being owned and ensuring quality through central QA run which ensure consistency across all collaterals being generated before handoff to another teamCollaborate with FE Logic designer on integration of Analog Circuit CBB into PHY level particularly in BMOD coding FEV SCAM and MSV validationCollaborate with BE Structural Design PV engineer on Analog Circuit timing model being generated to meet timing closure requirement at PHY level Collaborate with Platform Signal Integrity and Power Delivery team that using generated IBIS amp ICCT model for optimum platform solution
BSEE with 7 years relevant experience or Masters with 5 years relevant experience requiredEducation Focus should include integrated circuit design and analog designProven track record on design of high speed analog and mixed signal design for DDR4LP4DDR5LP5 DDR PHYs with involvement definition to productization on at least 2 full projectsGood understanding of design for yield and exposure to production challenges in latest technology process node Prefer design knowledge of 20nm and belowExperience with industry standard tools for Analog design such as Cadence ADE Spectre AMS verification FEV StarRC etcCross discipline knowledge in any of these areas such as Analog integration RTL System Verilog Static timing analysis concepts APR Floor planning Metal routing Power grid Memory IO training MRC and HASMAS specification documentationStrong written and oral communication skillsInside this Business Group
IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.

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