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Memory Modeling RTL Engineer

Location Bengaluru, India
Posted 14-August-2021
Memory Modeling RTL Engineer
The Device Development Group (DDG) Atom team is chartered with designing the latest Intel processors using the most advanced and innovative process technologies. The processors conceived, designed and developed by the team directly contributes to Intels leading processors used to create integrated hardware and software solutions such as processors, chipsets, graphics processors, motherboards, and networking components that deliver capabilities for security, manageability, performance, and energy efficiency. The agile team is at the forefront of the rapidly evolving digital world of computing by providing processor solutions and capabilities to efficiently manage data that is extensively integrated into all aspects of everyday life impacting how the world rapidly accesses, stores and uses data for daily personal and business applications.Role responsibilities include:Performs logic design, Register Transfer Level (RTL) coding, and simulation to generate cell libraries, functional units, and subsystems for inclusion in full chip designsParticipates in the development of Architecture and Microarchitecture specifications for the Logic componentsProvides IP integration support to SoC customers and represents RTL teamDevelop and deliver high-performance memories to internal/external customersWorking with memory circuit designers to understand and model advanced circuit features on current and future technology nodes.Developing memory RTL views for several front-end design contexts (simulation/UPF, emulation, ATPG, FPGA, GLS etc.) for register files, SRAMs and ROMs.Working with design automation team as needed to deploy tools/flows to validate said RTL views.Tailoring RTL views to meet customer requirements, developing the necessary automation to do so.


Bachelors with 6years or Masters of Science degree with 5years in Electrical Engineering, Computer Science, or Computer Engineering.

Expertise in programming languages such as C, Python, Ruby, or Tcl as well as experience in using the UNIX/Linux operating system

RTL Verilog, V2K, or System Verilog with a working knowledge of hardware modeling issues and logic debug environments

Modern energy-efficient/low-power logic design techniques, including those specifically applicable to high frequency optimization.

Demonstrated success in one or more of the following areas: Custom digital logic block design, synthesis of a digital logic block, which was integrated into a large SoC or IP or PV convergence (including static timing and power analysis)

Preferred Qualifications:

Prior knowledge and/or experience with developing front-end views required to support a memory vendor business model.

Familiarity with industry standard memory vendor compiler portfolios/capabilities including ATPG and array DFT requirements, power gating and redundancy options.

Familiarity with hardware modeling languages such as Verilog 95, SystemVerilog and programming languages like C, C, Perl, TCL.

Ability to multi-task, evaluate/prioritize requests from multiple customers and deliver on-time solutions in a fast-paced, technically demanding work environment.
Min 6 to 9 Years.

Awards & Accolades for MyTechLogy
Winner of
Top 100 Asia
Finalist at SiTF Awards 2014 under the category Best Social & Community Product
Finalist at HR Vendor of the Year 2015 Awards under the category Best Learning Management System
Finalist at HR Vendor of the Year 2015 Awards under the category Best Talent Management Software
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