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Post Si validation Security Engg. Manager

Location Bengaluru, India
Posted 09-September-2021
Description
Post Si validation Security- Engg. Manager
Our team is responsible for Silicon level HW architectural validation and accountable to find design implementation bugs through post si system level validation As a Post Silicon Validation Engineering Manager ( Client Microprocessor and Chipset Hardware), you are required to create Detail Validation strategy and plan, Resource requirement, Risk analysis You need to develop relationship with all the stakeholders - Program management and all HW/SW internal and external suppliers and ensure commitment for all receivables on time and with required quality; You are responsible for the development of strong technical team and drive continuous improvement on Quality and efficiency initiatives. You will be responsible for Validation and debug methodologies, track execution of validation plans/ coverage, and debug of failures. Requires broad understanding of multiple system areas and requires interfaces with Architecture, Design, and Pre-silicon Validation teams in improving post-silicon test content and providing feedback for future on-die debug features. You are focal point between a number of Architecture, Design, System software developers and Validation teams within Intel and across different sites.


Qualifications

Bachelors/Masters in Hardware Engineering or Electrical/ Electronics Engineering or Computer Engineering or Computer Science with minimum 12 years to 15 years -Domain Lead Manager position- of related work experience. Candidate Must have high degree of Hardware architecture/ microarchitecture experience in CPU/SoC/Chipset/and one of the subsystems areas given below Strong knowledge and skills of Intel IA (IA32 architecture with uArch debug knowledge of Intels Core and Uncore or equivalent architecture. Solid understanding of one of the following domain Industry spec, associated technologies and architecture: o USB architecture who familiar in USB Bulk/Interrupt/Isochronous transfer, Type of USB, Host/Device relationship, Transmission . o Knowledge of IA/ARM core and system level Power Management architecture who familiar in PMC feature, VID setting, Gate/Chip level power management transition state etc. Understanding of System Reset and Thermal related Validation expertise is a plus. o PCIe architecture who familiar in PCIe interconnect, link, Lane, Configuration, Interrupt, I/O Read/Write, PCIe Layer, Form Factor o Deep understanding of memory Controller / DDR 2/3/4 memory architecture and debug. LPDDR knowledge is a plus. o Deep understanding of Graphics, media, Audio, Camera interface, imaging and printing , flash storage technology architecture and debug. o Solid understanding of the Validation and Debug flows of a complex CPU Silicon: Knowledge on Validation/ Debug Flows and overall SOC Architecture. Pre-silicon Design / Validation knowledge is a value add. Good working knowledge in C/Python SW programming for content development and scripting. Knowledge of Verilog/VHDL and EDA design tools and pre si validation methodology is a plus. Excellent written and oral communications and experience working in a cross functional team environment are essential. Good Team Player and go to personality. Possess very good stakeholders management, Multitasking, ownership ability. Possess strong problem solving, analytical and debug skills.

Inside this Business Group
The everyday contributions of the Intel Validation Engineering (iVE) team are essential to retaining/regaining Intels product leadership. We validate, debug, and tune the newest designs and world-changing technologies that enrich the lives of every person on earth. We play a critical role in completing the PRQs of Intel products and in Intels ability to deliver the annual technology platforms in our roadmap.
Experience
Min 15 to 18 Years.

 
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