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Emulation Engineer

Location Hyderabad, India
Posted 02-December-2021
Description
The candidate should have a thorough knowledge of Cadence Palladium tool flow He should have a prior experience of validating designs using Palladium. Following technical skills are a must

Basic Job Deliverable: Knowledge of Verilog, System Verilog
Integration with Palladium speed bridges
Hands on working knowledge of SOC
Knowledge of Industry standard protocols like PCIe, USB, SATA, SPI, QSPI, I2C, RGMII, Display Port
Working knowledge of AXI4 and ARM processors
Very good debugging skills
Working knowledge of Xilinx tools and creating Vivado IPI designs
Hands on expertise in automation & regression frame work
Expertise in scripting like Perl, Tcl & Python
Should be able to do automation of Palladium builds and test


Qualification B.E

Experience 6-8 years
Experience
Min 6 to 8 Years.

 
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