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Senior Design Engineer 1

Location Hyderabad, India
Posted 22-August-2021
Description
Ownership of Synthesis and Static timing analysis of Large subsystem, hierarchical and full chip designs.
Interact closely with Design, DFX and Physical Design teams for understanding dependencies, providing feedback and alignment deliveries
Debug Synthesis, Timing QOR, SDC, Low power, Scan stitching issue
Deliver Timing Closed database for Tapeout including Noise, Signoff Checklists, Functional/ Timing ECOs
Create new and/or enhance synthesis/timing methodologies and develop proof of concept testcases, automate and work with CAD to roll out flows

Job requirements:

Should be an Expert with hands on experience in full chip / Subsystem /IP timing closure, Low Power Synthesis, constraints development
Must have knowledge on RTL/design understanding , Synthesis optimization, SDC, clocking, low power (UPF) and DFT
Must have good understanding for ASIC physical design flows, with various tools , understanding and scripting experience
Must have strong debugging skills- timing issues, SDC , clock propagation
Experience with developing flows, methodologies, jitter, spice simulation is a plus
Must Worked on multiple tapeouts and projects directly responsible for timing signoff


Education Requirements
BS/MS in electrical or electronics engineering

Years of Experience

3-5 years
Experience
Min 3 to 5 Years.

 
Awards & Accolades for MyTechLogy
Winner of
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Top 100 Asia
Finalist at SiTF Awards 2014 under the category Best Social & Community Product
Finalist at HR Vendor of the Year 2015 Awards under the category Best Learning Management System
Finalist at HR Vendor of the Year 2015 Awards under the category Best Talent Management Software
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