This course is a thorough introduction to the Verilog language. The emphasis is on writing Verilog model, both behavioral and structural source code and Register Transfer Level (RTL). This Sessions addresses targeting Xilinx FPGA devices . There is a lecture section for each main topic. This presents a basic foundation for the language. The Knowledge gained can be applied to any digital design by using a top-down or Bottom-up synthesis design approach. This course combines lectures with lab exercises to strengthen key concepts. You will also learn advanced coding techniques that will increase your overall Verilog.
The Main goal of this course is to make you familiar with developing a RTL Verilog model, both behavioral and structural, using as much of the language as possible, and writing a verification test cases and User constraints files for that model.
Who should take this course?
This course is Designed for designers who are new to Verilog and who wish to become familiar with the language with a particular emphasis on writing RTL code for synthesis. And Engineers who want to use Verilog effectively for modeling, design, and synthesis of digital designs.
At the end of my course, students will be able to :
After the course students with little Verilog knowledge will finish this course empowered with the ability to write efficient hardware designs and perform high-level HDL simulations. and
Ø Write RTL Verilog code for synthesis
Ø Write Verilog test fixtures or Test benches for simulation
Ø Target and optimize Xilinx FPGAs by using Verilog
Ø Run a timing simulation by using Xilinx ISim libraries
Ø Create and manage designs within the Xilinx Design Suite
Ø Correctly model combinational and sequential hardware blocks
Ø Write User constraints files for any FPGA board.
What will students need to know or do before starting the course? :
Ø Basic digital design knowledge
Ø Download the Xilinx ISE Design suite 14.4 System Edition and Install In to your System.
Ø Digilent NEXYS 2 Board WITH Spartan 3E -500E or 1200 E .