SystemVerilog Verification -3 : Build Your Random TestBench
Udemy
Course Summary
VLSI : Learn System Verilog Constraint Random Verification to build Random TestBench for SoC Verification
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Course Description
This course teaches the SystemVerilog language used in the VLSI industry for System-On-Chip design verification. This is primarily focusing on the reusable random testing features of SystemVerilog.
This course contains video lectures of 2 hours duration. It is stared by explaining what  is  Constraint Random Verification (CRV) and how it can be implemented in a SV TestBench. It explains the concepts of using random variables in a class and how to add different types of constraints to  to them.  Below summary of the topics covered in this course.
- Constraint Random Verification
- Random Variables
- Adding Constraints to Random Variables
- Controlling constraints, Weighted distribution, and Inline constraints
- Pre_randomize and Post_randomize
- Randcase
- Randsequence
- General SV TB StructureÂ
- Class Based SV TB Structure Â
- Coding Example of building a random TB
By taking this course, the you will be able to start using CRV support features in SystemVerilog for effective TestBench coding. This course will an excellent platform to grab the magical features of SystemVerilog to build reusable random who understand the basic of it.
