This course teaches the SystemVerilog language used in the VLSI industry forÂ System-On-ChipÂ design verification. This is primarily focusing on the reusable random testing features ofÂ SystemVerilog.
This course contains video lectures of 2Â hoursÂ duration.Â It is stared by explaining whatÂ Â is Â Constraint Random Verification (CRV) andÂ how it can be implemented in a SVÂ TestBench. It explains the concepts of usingÂ random variablesÂ in a class and how to add different types of constraints toÂ Â to them. Â Below summary of the topics covered in this course.
- Constraint Random Verification
- Random Variables
- Adding Constraints to Random Variables
- Controlling constraints, WeightedÂ distribution, and Inline constraints
- Pre_randomize and Post_randomize
- General SV TB StructureÂ
- Class Based SV TB StructureÂ Â
- Coding Example of building a random TB
By taking this course, the youÂ will be able to start using CRV support features inÂ SystemVerilog for effective TestBench coding.Â This course will an excellent platformÂ to grab the magical features of SystemVerilog to build reusable random who understand the basic of it.