Systemverilog course teaches the concepts of coverage analysis used in SoC/ASIC
Verification. This explains the complete concepts of using code coverage and
functional coverage as verification a metric
and teaches in detail how covergroups and covepoints can be written in Systemverilog
to enable functional coverage collection. This will enable a verification
Engineer to master functional coverage writing techniques which will help to do
good quality verification closure of the Design Under Test.
course is started by explaining the need for using coverage metric in verification
and the idea of code coverage and functional coverage in SV. It teaches the
functional coverage anatomy and explains the various forms of writing
them. Different forms of coverpoints and coverage bins in a covergrop are
explained in detail. Also It teaches cross coverage, coverage options and use of parameterized covergroups in depth.
taking this course, you will be able to start enabling functional coverage
in your SystemVerilog TB. This will be an excellent platform to master
functional coverage coding analysis techniques in SV.